The present invention relates to a wiring substrate, a semiconductor device, and a method for manufacturing the wiring substrate.
Electronic devices have been miniaturized while implementing more functions. As a result, the semiconductor devices used in such electronic devices have become smaller, while being more integrated and include more terminals. The reliability required for such semiconductor devices has also increased. Such a semiconductor device generally has a structure in which a semiconductor chip is mounted on a wiring substrate. Thus, the miniaturization and increased integration of a semiconductor chip has miniaturized and highly integrated connection terminals of the wiring substrate. A flip-chip mounting technique is thus often used for mounting on a semiconductor chip.
The flip-chip mounting technique forms an electrode terminal (bump), which including a projection, on the semiconductor chip, and electrically couples the bump directly to a pad exposed from a protective film (solder resist layer) of the chip mounting surface on the wiring substrate using a conductive material such as solder.
Further, in the flip-chip mounting technique, to insulate the joined portion of the semiconductor chip and the wiring substrate from the exterior and increase the strength of the joined portion, a resin referred to as an underfill is filled between the semiconductor chip and the wiring substrate. However, when the underfill resin has high fluidity, the underfill resin may spread on the wiring substrate over an area that is more than necessary and thereby contaminate other mounting pads. This lowers the yield of the semiconductor device. Accordingly, a wiring substrate may include a dam to block the underfill resin on a solder resist layer near a chip mounting region of the wiring substrate (refer, for example, to Japanese Laid-Open Patent Publication No. 2004-186213 and Japanese Laid-Open Patent Publication No. 5-283478).
FIG. 24(a) is a schematic plan view of a conventional semiconductor device, FIG. 24(b) is a schematic cross-sectional view of the semiconductor device taken along line A-A in FIG. 24(a), and FIG. 24(c) is a schematic cross-sectional view of the semiconductor device taken along line B-B in FIG. 24(a).
Referring to FIG. 24(b), the conventional semiconductor device includes a wiring substrate 5, a semiconductor chip 50, and an underfill resin 52.
The wiring substrate 5 includes a substrate main body 10, a wiring pattern 20 in the uppermost layer, an external connection pads 40, solder resist layers 90 and 91, and a dam 100. The semiconductor chip 50 mounted on the wiring substrate 5 includes a plurality of bumps 51 arranged on the periphery of a circuit formation surface of the semiconductor chip 50 (refer to the broken lines in FIGS. 24(b) and 24(c)).
The substrate main body 10 includes a core substrate II, a plurality of insulating layers 12 and 13, and wires 14 and 15, and vias 16 and 17. The wires 14 and 15 and the vias 16 and 17 are formed in the insulating layers 12 and 13, respectively. The wiring pattern 20 and the external connection pads 40 are electrically coupled to the wires 14 and 15 and the vias 16 and 17 of the substrate main body 10.
The wiring pattern 20 is arranged on the upper surface of the substrate main body 10. The wiring pattern 20 includes a pad 21 coupled to each bump 51 of the semiconductor chip 50.
The solder resist layer 90 is arranged on the upper surface of the substrate main body 10. An opening 90a is formed in the pad formation region of the solder resist layer 90 to expose the pads 21. Specifically, since the pads 21 are arranged in a frame-shaped manner along the periphery of the semiconductor chip 50 in accordance with the layout of the bumps 51 of the semiconductor chip 50 (see FIG. 24(a)), the opening 90a extends in a frame-shaped manner. The opening 90a extends through the solder resist layer 90 at the portion corresponding to the pad formation region. The wiring pattern 20 arranged in the pad formation region and exposed from the opening 90a forms the pads 21. The portions exposed from the opening 90a other than the pads 20 are parts of an insulating layer 12 formed under the wiring pattern 20.
As shown in FIG. 24(a), the dam 100 surrounds a chip mounting region CA, in which the semiconductor chip 50 is mounted, on the solder resist layer 90. The dam 100 is formed so that its inner edge extends along and outward from the periphery of the chip mounting region CA. The dam 100 blocks the underfill resin 52 so that the underfill resin 52 that flows out from between the wiring substrate 5 and the semiconductor chip 50 when filling the underfill resin 52 is not more than necessary.
The semiconductor chip 50 is flip-chip-coupled to the wiring substrate 5. In other words, the semiconductor chip 50 is electrically coupled to the pad 21 of the wiring substrate 5 by the bumps 51 arranged on the circuit formation surface of the semiconductor chip 50.
The underfill resin 52 is arranged in a gap between the wiring substrate 5 and the semiconductor chip 50. The underfill resin 52 increases the coupling strength of portions coupling the bumps 51 and the pads 21 and also prevents corrosion of the wiring pattern 20 and the occurrence of electro-migration. Thus, the underfill resin 52 maintains the reliability of the wiring pattern 20.
A method for manufacturing the above-described semiconductor device will now be described with reference to FIGS. 25 and 26.
In the semiconductor device manufacturing method shown in FIGS. 25 and 26, a core substrate ii shown in FIG. 25(a) is used. The core substrate II is manufactured by forming through holes 10a in a copper clad laminated (CCL) plate. Then, the walls of the through holes 10a are plated to electrically couple the two opposite surfaces of the core substrate 11. Afterward, wires 14 and 15 are formed by performing a subtractive process.
The insulating layers 12 and 13 are formed on the two surfaces of the core substrate ii, as shown in FIG. 25(b). Next, as shown in FIG. 25(c), openings 12a and 13a are formed in the insulating layers 12 and 13 at predetermined locations using, for example, a laser, to expose ends of the wires 14 and 15.
Subsequently, after a desmear process is performed, as shown in FIG. 25(d), a seed layer S1 is formed to cover the insulating layer 12 and the wires 14, and a seed layer S2 is formed to cover the insulating layer 13 and the wires 15. The seed layers S1, S2 are formed by performing electroless copper plating or sputtering.
Next, a semi-additive process is performed to form the wiring pattern 20 and a wiring pattern on the lower surface of the core substrate ii. Further, the vias 16 and 17 are formed to respectively extend through the insulating layers 12 and 13. More specifically, referring to FIG. 26(a), a 25 resist having an opening pattern shaped in correspondence with the wiring pattern 20 is formed on the seed layer SI, and the vias 16 and the wiring pattern 20 are formed by performing electrolytic copper plating that uses the seed layer S1 as a power supply layer. The wiring pattern on the lower surface of the core substrate ii and the vias 17 are formed in the same manner as the vias 16 and the wiring pattern 20. After formation of the vias 16 and 17, the wiring pattern 28, and the wiring pattern on the lower surface of the core substrate II, the resist and the unnecessary seed layers S1 and S2 are removed.
The solder resist layer 90 is then formed to cover the wiring pattern 20. Then, photolithography is performed to expose and develop the solder resist layer 90 to form the opening 90a, which is shown in FIG. 26(b). This exposes parts of the wiring pattern 20 as the pads 21. The solder resist layer 91 is formed to cover the wiring pattern formed on the lower surface of the core substrate II. Then, photolithography is performed to form openings 91a, which is shown in FIG. 26(b). This exposes parts of the wiring pattern as the external connection pads 40.
Referring to FIG. 26(c), the dam 100, which has a predetermined pattern, is then formed on the solder resist layer 90. The dam 100 is formed from, for example, a resin having the same composition as the resin forming the solder resist layer 90. The dam 100 may be formed by performing a photolithography process, a printing process, a process for laminating a thin plate having a predetermined shape, or the like. When performing photolithography, a photosensitive solder resist is exposed and developed to form a predetermined pattern. When performing the printing process a print mask is used to print only necessary portions with the resin material.
Referring to FIG. 26(d), the semiconductor chip 50 is flip-chip-bonded to the wiring substrate 5. More specifically, the bumps 51 of the semiconductor chip 50 are bonded to the pads 21 of the wiring substrate 5. Then, the underfill resin 52 is filled between the flip-chip-bonded wiring substrate 5 and semiconductor chip 50. The underfill resin 52 flows between the wiring substrate 5 and the semiconductor chip 50 and is then cured and solidified by undergoing a heating process. This protects the coupling portions of the pads 21 and bumps 51 from the exterior and improves the mounting reliability. In this state, even when the underfill resin 52 flows outward from the pad formation region, the dam 100 blocks the underfill resin 52. This prevents the underfill resin 52 from contaminating other mounting pads.
However, the formation of the dam 100 requires additional dam material (resin material) and additional manufacturing processes. This raises the manufacturing cost and increases the number of steps for forming the dam 100.
The viscosity of the underfill resin 52 may be increased to prevent excessive flow of the underfill resin 52 and eliminate the need for the formation of the dam 100. In this case, however, the increase in the viscosity of the underfill resin 52 makes it difficult to fill the underfill resin 52. As a result, the distance between the semiconductor chip 50 and the wiring substrate 5 must be increased to facilitate the filling of the underfill resin 52. The distance may be increased by increasing the amount of solder formed on the pads 21 so that the semiconductor chip 50 can be easily coupled to the bumps 51. However, for recent semiconductor devices, which are miniaturized and highly accurate, the amount of solder cannot be increased because the pitch between pads has narrowed and the pitch between bumps has narrowed accordingly. More specifically, when more solder is used, the solder causes short-circuiting between adjacent pads, namely, solder bridge. Thus, the amount of solder cannot be increased, and the distance between the semiconductor chip 50 and the wiring substrate 5 cannot be increased. Thus, the filling of the underfill resin 52 cannot be facilitated. As a result, when the viscosity of the underfill resin 52 is high, filling defects or the like of the underfill resin 52 may occur. This would lower the electrical coupling reliability between the semiconductor chip 50 and the wiring substrate 5 and reduce the yield of semiconductor devices.
The problem described above occurs not only in a wiring substrate including pads laid out along the periphery of the circuit formation surface but also, for example, in a wiring substrate including pads laid out in matrix array.